In a semiconductor device, semiconductor elements thereof have been miniaturized, as the capabilities of processing techniques have progressed. However, further miniaturization of the semiconductor elements has recently reached the limits of pattern width miniaturization, based on the physical (optical) limit of optical exposure used in photolithography. However, multi-patterning methods, such as double patterning, which are capable of obtaining a line-and-space (L/S) pattern having a pattern and spacing width below the optical limits of lithographic exposure resolution, has attracted much attention.
One such double patterning technique is a sidewall transfer technique, wherein a sacrificial material is pattern etched, a masking material is deposited into the removed portions of the sacrificial material and is further etched in the region between remaining sacrificial material locations to leave a thin masking layer only on the sidewalls of the sacrificial material, and then the sacrificial material is removed, leaving the very thin masking layer behind to serve as a process mask for further processing. However, where the line-and-space pattern to be formed using this technique has curving or “bending” regions, the resultant line structures in the bending region become thicker than in other portions of the pattern, such as where the pattern includes generally parallel straight lines. As a result, wiring patterns formed using this technology may come into contact with each other in locations where the pattern bends, and thus short-circuit to one another. For this reason, the disposition of a dummy pattern for suppressing the occurrence of such an error is considered. That is, a plurality of wiring patterns are bent and expanded and a dummy pattern is disposed at a portion where a single wiring pattern is disposed so that a state where a single wiring pattern is disposed is not provided, thereby suppressing an error occurring due to processing conversion.
On the other hand, as a configuration for achieving an insulation state between wiring patterns, an air gap structure using air or a vacuum state as an insulator is adopted. This is a technique of forming an insulating film so as to connect and cover upper portions of wiring patterns without filling spaces between the wiring patterns to thereby form an “air” gap or vacuum gap, where the overlying capping dielectric layer is deposited in vacuum, gap between the wiring patterns.
Therefore, in the technique of forming the air gap between the wiring patterns as described above, the air gap is formed in a portion in which the dummy pattern is provided. For this reason, when processing of the wiring patterns is performed, the air gap may be opened when removing the dummy pattern. When a portion in which the air gap is opened is generated, there is a problem in that the etch chemical(s) enter the air gap from the opened portion in a subsequent process.